1. Field of the Invention
The present invention generally relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus including a multilayer wiring structure.
2. Description of the Related Art
In recent years and continuing, operating speed is increased by miniaturizing a semiconductor apparatus in accordance with scaling law. In recent high density semiconductor integrated circuit apparatuses, a multilayer wiring structure is, in general, used for wiring between respective semiconductor apparatuses. With the multilayer wiring structure, however, the proximal arrangement of the wiring patterns in the multilayer wiring structure causes wire delay from parasitic capacity between the wiring patterns. The parasitic capacity is in inverse proportion to the distance between the wiring patterns and is proportional to the dielectric constant of an insulator between the wiring patterns.
Accordingly, in order to solve the problem of wire delay in the multilayer wiring structure, an interlayer dielectric having a low dielectric constant is proposed to be used as the interlayer dielectric so as to reduce the parasitic capacity. The dielectric constant is approximately 4 in a case of a conventional example using a CVD-SiO2 film as the interlayer dielectric. For further reducing the dielectric constant, the dielectric constant may be, at most, approximately 3.3–3.5 in a case of using SiOF which is a CVD-SiO2 film with fluorine added. This reduction of dielectric constant, however, is insufficient for satisfying the current high density semiconductor integrated circuits and causes difficulty in obtaining necessary operating speed.
Therefore, in order to further reduce the dielectric constant, a porous insulating film formed by a spin coating method is proposed to be used as the interlayer dielectric having a low dielectric constant. In obtaining the porous insulating film, a coating material with an organic resin material added that evaporates or decomposes from heat is spin coated on an insulating film. Then, the coating material is heated for evaporating or decomposing materials including, for example, the organic resin material. As a result, the insulating film is formed into the porous insulating film.
By forming the insulating film into a porous insulating film, the dielectric constant of the insulating film can be reduced to 2.5 or less.
The above-described wire delay is proportional to the product of the wire resistance and the parasitic capacity between the wires. Therefore, in recent years, Cu that has low resistance is used as an alternative to the conventional wiring material of Al.
FIG. 1 is a cross-sectional view showing a portion of a semiconductor apparatus 100 using the above-described porous insulating film.
With reference to FIG. 1, the semiconductor apparatus 100 includes an element area separated by an element separating film 102 on a Si substrate 101. A gate insulating film 104A disposed on the Si substrate 101, a gate electrode 104 formed on the gate insulating film 104A, and diffusion layers 105A, 105B formed on corresponding sides of the gate electrode 104 are formed on the element area.
The side walls of the gate electrode 104 are covered by corresponding side wall insulating films 103A and 103B. Furthermore, an interlayer dielectric 106 is formed as a PSG (phosphosilicate glass) film on the Si substrate in a manner covering the gate electrode 104 and the side wall insulating films 103A, 103B.
A porous insulating film 110, being an interlayer dielectric having low dielectric constant, is formed on the interlayer dielectric 106 via a stopper film 107. A Cu wiring part 117 and a barrier film 117A formed in a manner surrounding the Cu wiring are provided in the porous insulating film 110.
The Cu wiring part 117 is electrically connected to the diffusion layer 105B via a contact plug 108 formed in the interlayer dielectric 106.
A protective film 111 and a stopper film 112 are formed on the porous insulating film 110. Furthermore, another porous insulating film 113 including a Cu plug part 118 and a barrier film 118A surrounding the Cu plug part 118 is formed on the stopper film 112.
The Cu plug part 118 is configured to be electrically connected to the Cu wiring part 117 via a barrier film 118A.
Furthermore, a stopper film 114 is formed on the porous insulating film 113. Another porous insulating film 115, which includes a Cu wiring part 119 and a barrier film 119A surrounding the Cu wiring part 119, is formed on the stopper film 114. Furthermore, a protective film 116, which is used during etching of the porous insulating film 115, is formed on the porous insulating film 115.
The Cu wiring part 119 is configured to be electrically connected to the Cu plug 118.
Since the semiconductor apparatus 100 shown in FIG. 1 employs a combination of porous insulating films (being interlayer dielectrics with low dielectric constant) and Cu wiring patterns (having low wire resistance), the semiconductor apparatus 100 has little wire delay and is able to operate at high speed.
The configuration shown in FIG. 1, however, is subject to problems such as disconnection/deformation of the Cu wiring in the multilayer wiring structure and damaging of the porous insulating film especially in a case where strict miniaturization is executed under a design rule of approximately 0.1 μm.
FIG. 2 is a perspective view showing a connected state of the Cu wiring parts 117, 119 and the Cu plug part 118 in the configuration shown in FIG. 1. It is to be noted, however, that the porous insulating film surrounding the Cu wiring parts 117, 119 and the Cu plug part 118 is not shown in FIG. 2.
With reference to FIG. 2, the Cu wiring parts 117 and 119, for example, are formed substantially parallel to the Si substrate 101, and have a volume which is greater than that of the Cu plug part 118. The Cu plug part 118 has a substantially cylindrical shape, has a cross-sectional area which is smaller than that of the Cu wiring parts 117, 119, and is disposed in a manner interposed between the Cu wiring parts 117, 119.
With the semiconductor apparatus 100 having the above-described configuration, stress transmitted via the Cu tends to concentrate at the Cu plug part 118. Furthermore, the semiconductor apparatus 100 has a low elastic modulus owing to the porous insulating film 113 serving as the insulating film surrounding the Cu plug part 118 and to the hole in the porous insulating film 113. Therefore, the porous insulating film 113 is easily deformed by the stress applied thereto and leads to a problem of the stress concentrating at the Cu plug part 118.
FIG. 3 is a diagram showing simulation results for evaluating stress in the Cu wiring parts and the Cu plug part (via plug) in a direction X substantially perpendicular to the Si substrate 101. In this case, calculation is performed under conditions where the value of the elastic modulus of the porous insulating film surrounding the Cu wiring parts and the Cu plug part is set to 5 GPa and the value of the hardness thereof is set to 0.6 GPa.
With reference to FIG. 3, the stress applied to the Cu wiring parts is greater than the stress applied to the Cu plug part. This shows that stress is concentrated in the Cu plug part in a multilayer wiring structure using Cu material.
With the configuration shown in FIG. 1, problems such as disconnection/deformation of the Cu plug part and damaging of the porous insulating film due to the deformation of the Cu plug part become apparent during a process of forming a contact pad on the porous insulating film 115 via a cap layer and wire bonding a wire to the contact pad.
Furthermore, the problems of disconnection/deformation of the Cu plug part and damaging of the porous insulating film may also be caused, for example, by stress from superposing the multilayer wiring or by thermal stress.
One reason for these problems is that the elastic modulus of the porous insulating films surrounding the Cu wiring parts and the Cu plug part is small compared to that of the inorganic insulating films (e.g. CVD-SiO2 film). Another reason is that stress tends to concentrate on the Cu plug part. The problem of deformation and disconnection of the multilayer wiring structure is particularly critical with respect to the stress created during the wire bonding process.